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Samsung Electronics is placing high-bandwidth memory directly on top of AI processors as part of a 3D memory architecture push designed to lower power consumption and deliver faster data transfers, according to a news report by The Korea Herald.
The tech giant unveiled concept models of two 3D architectures, dubbed zHBM and zNAND-O, at the Future of Memory and Storage 2026 event held at the Santa Clara Convention Centre in California. Samsung described both concept models as industry firsts. Traditional high-bandwidth memory packages sit alongside graphics processing units and other AI accelerators on the same plane. The zHBM architecture positions memory directly above the processor, reducing the physical distance required for data movement. As per the news report, the design aims to reduce data bottlenecks in AI systems, where accelerators continuously transfer large volumes of data to and from memory. Samsung said a next-generation interface system incorporating zHBM could deliver up to eight times the performance of HBM5, the eighth-generation HBM. Energy efficiency could improve by as much as threefold. The company also said advanced wafer bonding technology could also cut thermal resistance by more than half compared with HBM5, addressing one of the main challenges of vertically stacking high-performance memory and processors. As per the news report, the architecture allows tailoring to specific AI systems through an interlayer located between memory and accelerator chips. Incorporating customer-specific intellectual property, this interlayer can expand memory capacity or improve processor performance depending on setup requirements. Samsung indicated it will work alongside customers to optimize connections between AI processors and memory to enhance zHBM performance, though no commercial release timetable was disclosed. The news report mentioned that Samsung is also expanding its 3D architectural approach into NAND flash memory. The zNAND-O solution, currently under development, combines Samsung's V-NAND stacking technology with through-silicon vias, stacking four or eight semiconductor dies vertically into a single package. The designation "O" indicates a focus on on-device AI applications, where processing occurs locally rather than on remote servers. Vertical die stacking reduces physical space requirements while raising data-loading bandwidth and lowering response times for real-time local workloads. At the same event, Samsung unveiled its 10th-generation V10 BV-NAND technology featuring over 400 vertically stacked memory-cell layers. Described as the industry's first V-NAND design to pass the 400-layer threshold, the structure packs more memory cells into the same footprint to increase capacity, speed, and energy efficiency. The launch comes 13 years after Samsung debuted its initial V-NAND technology at the same conference, with the new architectures aimed at meeting rising demands across AI infrastructure and high-performance computing. (ANI)
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