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Taiwan Semiconductor Manufacturing Co. (TSMC) unveiled its next-generation A13 process at its North America Technology Symposium in California on Wednesday.
The world's largest contract chipmaker stated that it was targeting volume production for the new technology in 2029. The announcement came during the company's largest annual customer forum, which was held in Santa Clara under the theme "Expanding AI with Leadership Silicon." According to a report by Focus Taiwan, the new A13 process was aimed at meeting the growing demand for artificial intelligence, high-performance computing, and mobile applications. The company used the symposium to showcase its latest services and technological advancements designed to support the next generation of semiconductor design. The report mentioned that in a statement, TSMC Chairman and CEO, C.C. Wei, said that customers expect advanced nodes like the A13 to be ready for volume production when next-generation designs require them, adding the company continues to lead in chip density, performance and power efficiency. The A13 process improved on the previous A14 node by shrinking the chip area by 6 per cent while maintaining full design-rule compatibility. This allowed for a rapid migration to nanosheet transistor technology. TSMC noted that additional gains in performance and power efficiency were achieved through design-technology co-optimization. At the same symposium, the company also previewed its A12 process. This technology featured a "super power rail" architecture to provide backside power delivery for AI and high-performance computing applications. Production for the A12 was slated for 2029. Additionally, within its 2-nanometer platform, the N2U was expected to deliver a 3-4 per cent speed increase or an 8-10 per cent reduction in power use compared with the N2P. Production for the N2U was expected in 2028. Regarding advanced packaging, the report highlighted that TSMC announced it was expanding its CoWoS technology. The company planned to scale the technology from 5.5 times reticle size to 14 times, which allowed for the integration of approximately 10 compute dies and 20 high-bandwidth memory stacks. Production for this expansion was planned for 2028, while larger CoWoS and wafer-scale SoW-X were targeted for 2029. The company also advanced its SoIC 3D stacking capabilities. This included A14-to-A14 stacking by 2029, which offered 1.8 times the input/output density of 2nm-based SoIC. Furthermore, the COUPE photonics engine was set to reach a key milestone, with co-packaged optics entering production in 2026. This was expected to double power efficiency and cut latency by 90 per cent. For the automotive and edge AI sectors, the report noted that TSMC introduced the N2A node. This was the company's first nanosheet-based automotive node, with AEC-Q100 certification expected in 2028. (ANI)
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